1. Field
The present invention relates to the field of semiconductor memory devices, and more particularly to a memory core that has small core conjunction area, and to a semiconductor memory device having the memory core.
2. Description of the Related Art
Semiconductor memory devices are used in various electronic products and applications.
FIG. 1 is a diagram illustrating a layout of a memory core in a conventional semiconductor memory device. Referring to FIG. 1, the memory core includes memory cell arrays, sense amplifiers SA, sub word-line driving circuits SWD, and core conjunction blocks CONJ. Generally, circuit blocks included in the memory core are arranged as shown in FIG. 1.
FIG. 2 is a block diagram illustrating a more detailed view of the memory core shown in FIG. 1. Referring to FIG. 2, a word-line enable signal generating circuit 12 disposed in the core conjunction block 10 generates a first sub word-line control signal PXIB and a second sub word-line control signal PXID. A first sub word-line driving circuit 20 generates a first word-line driving signal WL1 based on a first main word-line driving signal NWE1, the first sub word-line control signal PXIB and the second sub word-line control signal PXID. A second sub word-line driving circuit 30 generates a second word-line driving signal WL2 based on a second main word-line driving signal NWE2, the first sub word-line control signal PXIB and the second sub word-line control signal PXID. A first memory cell array 40 operates in response to the first word-line driving signal WL1, and a second memory cell array 50 operates in response to the second word-line driving signal WL2.
The transmission speed of input data and output data of a semiconductor memory device, such as a dynamic random access memory (DRAM), is ever increasing. As the speed of the input data and output data increases, the speed of a memory core has to be increased. Generally, the speed of a memory core may be increased by increasing the number of input/output lines (10 lines). When the number of 10 lines is increased, the size of a control circuit is increased. The control circuit is usually arranged in the core conjunction region. Therefore, the area of the core conjunction region is increased as the speed of a memory core increases.